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Evaluation Board & IP Core V-by-One HS IP Core

拡大表示

V-by-One® HS is a standard developed by THine Electronics, Inc. to meet the needs of flat-panel display markets that require higher frame rates and higher resolutions than ever before.
Using the V-by-One HS IP cores for Xilinx FPGA provided by Tokyo Electron Devices, we are able to significantly reduce the number of cables in the device, the cost of developing it, and the time required for developing it.

Product specifications and features

Features Transmission rate up to 3.75Gbps per data lane for Kintex-7 FPGA
Supports 1, 2, 4, and 8 data lanes (Customizable in 16, 32 data lane compatible consigned development)
Flexible setting of swing width and pre-emphasis function
Flexible Implementation and Package Compatibility
Core specifications Transmission rate up to 3.75Gbps per data lane for Kintex-7 FPGA
Supports 1, 2, 4, and 8 data lanes (Customizable in 16, 32 data lane compatible consigned development)
Flexible setting of swing width and pre-emphasis function
Flexible Implementation and Package Compatibility
Supporting FPGA Kintex UltraScale(GTH)
Virtex-7(GTH)
Kintex-7(GTX)
Artix-7(GTP)

Product Block Diagram

Product Block Diagram

Resolution and Operation Specifications

Resolution Refresh rate
(pixel clock)
Color bit width Number of data lanes
HD 60Hz(74.25MHz) 18/24/30/36bit 1
120Hz(148.5MHz) 18/24/30/36bit 2
240Hz(297MHz) 18/24/30/36bit 4
Full-HD 60Hz(148.25MHz) 18/24/30/36bit 2
120Hz(297MHz) 18/24/30/36bit 4
240Hz(594MHz) 8/24/30/36bit 8
4K2K 60Hz(594MHz) 18/24/30/36bit 8
120Hz(1188MHz) 18/24/30/36bit 16
240Hz(2376MHz) 18/24/30/36bit 32

Link system diagram

Link system diagram

Order information

Product Model Number Project license
TIP-VBY1HS-PROJ
Deliverables V-by-One HS IP cores (project licensing)
User Manual
Remarks Documents downloaded from the website dedicated to buyers on the TED Support Web

Related products

Documents

Data Sheet
User Manual

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Post-purchase technical support

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V-by-One HS IP Core

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